Conference Papers and Journals by Eric Pauer

Listed below are Eric's publications and conference papers.   For papers published after 1995, electronic versions are available in Adobe PDF format.

Defense Support to Civil Authorities – Federal Military Assistance, Vermont Emergency Preparedness Conference, Fairlee, VT, September 2017.

Surveillance Transmitter of the Future, Office of National Drug Control Policy (ONDCP) Conference, San Diego, CA, July 2003.

Environment for Implementing DSP Algorithms in Reconfigurable Hardware, Fourth Annual Workshop on High Performance Embedded Computing (HPEC), Lexington, MA, September 2000.

Algorithm Analysis and Mapping Environment for Adaptive Computing Systems, Eighth ACM International Symposium on Field-Programmable Gate Arrays (FPGA 2000), Monterey, CA, February 2000.

High Performance Scalable Computing Performance Modeling Using Ptolemy, IASTED International Journal of Modelling and Simulation, Volume 19, Number 4, 1999.

An FPGA Based Adaptive Computing Implementation of Chirp Signal Detection, Military and Aerospace Applications of Programmable Devices and Technologies (MAPLD), Laurel, MD, September 1999.

An Environment for Migrating Dataflow Algorithms into Adaptive Computing Hardware, Third Annual Workshop on High Performance Embedded Computing (HPEC), Lexington, MA, September 1999.

Algorithm Analysis and Mapping Environment for Adaptive Computing Systems - Further Results, 7th Annual IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM), Napa, CA, April 1999.

Adaptive Computing System Design and Implementation using the ACS Domain, Ptolemy Miniconference, University of California, Berkeley, CA, February 1999.

Rapid Implementation of Mathematical and DSP Algorithms in Configurable Computing Devices, SPIE International Symposium on Voice, Video, and Data Communications, Boston, MA, November 1998.

Algorithm Analysis and Mapping Environment for Adaptive Computing Systems, Second Annual Workshop on High Performance Embedded Computing (HPEC), Lexington, MA, September 1998.

VHDL-based Performance Modeling for 2D and 3D Infrared Search and Track Processing, SPIE International Symposium on Optical Science, Engineering and Instumentation, San Diego, CA, July 1998.

A Performance Modeling Framework Applied to Real Time Infrared Search and Track Processing, IEEE VHDL International Users Forum (VIUF), Crystal City, VA, October 1997.

Multiprocessor System Development for High Performance Signal Processing Applications, IEEE International Workshop on Rapid System Prototyping (RSP), Chapel Hill, NC, June 1997.

High Performance Scalable Computing Performance Modeling Using Ptolemy, IASTED International Conference on Modelling and Simulation, Pittsburgh, PA, May 1997.

High Performance Scalable Computing Performance Modeling Using Ptolemy, Ptolemy Miniconference, University of California, Berkeley, CA, March 1997.

An Architectural Trade Capability Using the Ptolemy Kernel, IEEE International Conference on Acoustics, Speech, and Signal Processing (ICASSP), Atlanta, GA, May 1996.

A DSP Array Processor for Real-Time Signal Processing, International Conference on Signal Processing Applications and Technology (ICSPAT), Boston, MA, November 1992.

Characterization of Wide-Bandwidth HF Digitizing Receivers, IEEE Military Communications Conference (MILCOM), McLean, VA, November 1991.

A DSP Array for Real-Time Adaptive Sidelobe Cancellation, SPIE International Symposium on Optical Applied Science and Engineering, San Diego, CA, July 1991.

Last update to these pages:  June 23, 2020


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